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DATA SHEET
PD6461, 6462
CMOS LSI CHIP FOR CAMCORDER ON-SCREEN CHARACTER DISPLAY (12 ROWS x 24 COLUMNS)
MOS INTEGRATED CIRCUIT
The PD6461, 6462 are CMOS LSI chips designed to provide on-screen character display for camcorders. When combined with a microcontroller, the PD6461, 6462 control the display of the characters displayed in the viewfinder (count, time, date, etc.) and the recording of characters onto video tape (time, date, etc.). Each character is created using 12 (width) x 18 (height) dots. Kanji characters and graphic symbols can also be displayed by using two or more characters. The PD6461, 6462 are compatible with color viewfinders and can output character signals to three channels, the RGB channel for the color viewfinder and the VC1 and VC2 channels for the recording system and monitor terminal. The PD6461, 6462 also have a power-on clear function and video RAM batch clear command, enabling the number of operations assigned to the microcontroller to be reduced.
FEATURES
* Maximum number of characters: 12 rows x 24 columns (288 characters) * Number of character patterns : 256 (PD6461)/128 (PD6462) (stored in ROM). Each pattern can be changed by specifying a mask code option. * Character size * Number of character colors * Background : One dot per line or one dot per two lines (field) :8 : No background, minimum background, or overall background can be selected for the entire screen, together with rimming ON/OFF function. Any one of 8 different colors is selectable as the background color and together with the rim color (black or white) selectable per screen. * Dot matrix * Blinking * Reversed characters * Character signal output : Each character consists of 12 (width) x 18 (height) dots. There is no gap between adjacent characters. : Blinking can be turned on/off for each character. The blinking ratio is 1:1. The blinking frequency can be selected from approx. 1 Hz, 2 Hz, and 0.5 Hz for the entire screen. : Specified characters can be displayed in reverse video. : Character signals can be output to three channels. Output mode (1) (RGB + BLK, VC1 + VBLK1, and VC2 + VBLK2) or output mode (2) (R + RBLK, B + BBLK, and G + GBLK) can be selected by specifying a mask option. For output mode 1, three output formats are available for the VC1 and VC2 channels (options A, B, and C). * Clearing of video RAM : Video RAM batch clear command and power-on clear function by specifying a mask option.) * Supply voltage : Low-voltage operation possible (supply voltage range: 2.7 to 5.5 V) * Interface with a microcontroller : 8-bit serial input supporting variable word length (LSB first or MSB first can be selected
The information in this document is subject to change without notice. Document No. S13320EJ1V1DS00 (1st edition) Date Published November 1998 N CP(K) Printed in Japan
The mark
shows major revised points.
(c)
1998
PD6461, 6462
ORDERING INFORMATION
Part number Package 20-pin plastic shrink SOP (300 mil) 24-pin plastic SOP (375 mil) 20-pin plastic shrink SOP (300 mil)
PD6461GS-xxx PD6461GT-xxx PD6462GS-xxx
Remarks 1. xxx is a ROM code suffix.
2. NEC's standard models are the PD6461GS-101/102, PD6462GS-001. For the details of the character generator ROM, refer to 5. CHARACTER PATTERNS.
PD6461GS-101: MSB first/Specified in three-line units/RGB+3BLK/Option B/LC oscillation PD6461GS-102: MSB first/Specified in three-line units/RGB+VC1+VC2/Option B/LC oscillation PD6462GS-001: MSB first/Specified in three-line units/RGB+VC1+VC2/Option C/LC oscillation
2
BLOCK DIAGRAM
TEST VDD Data input shift register Instruction decoder Control signals GND PCL CS Horizontal address register for display position
DATA CLK
Character size register
Write address counter
Video RAM
Data selector
CKOUT
Horizontal size counter
Horizontal position counter
Horizontal address counter
Character data 8 bits x 288 words
Color data 3 bits x 288 words
Blink data 1 bit x 288 words
Reverse data 1 bit x 288 words
Output specification data 1 bit x 288 words
Background control data register
Display control data register
OSCIN Oscillator
Vertical address register for display position
OSCOUT
Character generator ROM 12 x 18 bits x 256 words (PD6461) / x 128 words (PD6462)
Hsync
Synchronization protection circuit
Vertical size counter
Vertical position counter
Vertical address counter Output controller
Vsync
PD6461, 6462
VR VG VB VBLK VC1 BLK1 VC2 BLK2 (BBLK) (BBLK) (RBLK)
Remark Signals in (
) are set by a mask option (RGB + RGB compatible blanking).
3
PD6461, 6462
PIN CONFIGURATION (TOP VIEW)
20-pin plastic shrink SOP (300 mil)
PD6461GS-xxx PD6462GS-xxx
CLK CS DATA PCL VDD CKOUT OSCOUT OSCIN TEST GND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
Hsync Vsync VB VG VR VBLK (BBLK) VC2 (GBLK) BLK2 (RBLK) VC1 BLK1
24-pin plastic SOP (375 mil)
PD6461GT-xxx
CLK CS N.C. DATA PCL VDD CKOUT OSCOUT OSCIN TEST GND N.C.
1 2 3 4 5 6 7 8 9 10 11 12
24 23 22 21 20 19 18 17 16 15 14 13
Hsync Vsync N.C. VB VG VR VBLK (BBLK) VC2 (GBLK) BLK2 (RBLK) VC1 BLK1 N.C.
Remarks 1. xxx indicates a ROM code suffix. 2. Signals in ( ) are set by a mask option (RGB + RGB compatible blanking).
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PD6461, 6462
BBLK CKOUT CLK CS DATA GBLK GND Hsync N.C. OSCIN OSCOUT PCL RBLK TEST VB VBLK VC1, VC2 VDD VG VR Vsync : Blanking B : Clock Output : Clock Input : Chip Select : Data Input : Blanking G : Ground : Horizontal Synchronous Signal Input : No Connection : Oscillator Input : Oscillator Output : Power-on Clear : Blanking R : Test : Character Signal Output : Blanking Signal Output for VR, VG, VB : Character Signal Output 1, 2 : Power Supply : Character Signal Output : Character Signal Output : Vertical Synchronous Signal Input
BLK1, BLK2: Blanking Output 1, 2
5
PD6461, 6462
PIN FUNCTIONS
Pin No.Note 1 SymbolNote 2 1 CLK FunctionNote 2 Clock input Description Input pin for the data read clock. The data input to the DATA pin is read at rising edges of the clock. Serial transfer is accepted when this pin is low. Input pin for control data. Data is read in synchronization with the clock input to the CLK pin. Pin used for the power-on clear function. After power-on, set this pin from low to high to initialize the IC. Power supply pin N-ch open-drain output pin used to check the oscillation frequency Input and output pins for the oscillator for generating a dot clock. Connect the oscillation coil and capacitors to these pins. (When an external clock input is selected by specifying a mask option, input an external clock (synchronized with Hsync) to the OSCIN pin. Leave the OSCOUT pin open.) 9 (10) TEST Test pin Pin used for testing the IC. Usually, connect this pin to ground. The IC cannot enter test mode while this pin is connected to ground. Connect this pin to the system ground. Pin used to output the blanking signal for the video signal output from the VC1 pin. The blanking signal is high active. (When RGB compatible blanking has been selected by specifying a mask option, this pin outputs the logical OR of RBLK, GBLK, and BBLK.) Pin used to output a high-active character signal. (When RGB compatible blanking has been selected by specifying a mask option, this pin outputs the logical OR of VR, VG, and VB.) Pin used to output the blanking signal for the video signal output from the VC2 pin. The blanking signal is high active. (This pin outputs the blanking signal for the video signal output from the VR pin. The blanking signal is high active.) Pin used to output a high-active character signal. (This pin outputs the blanking signal for the video signal output from the VG pin. The blanking signal is high active.) Pin used to output the blanking signal for the video signals output from the VR, VG, and VB pins. The blanking signal is high active. (This pin outputs the blanking signal for the video signal output from the VB pin. The blanking signal is high active.) Pins used to output high-active character signals.
2 3 (4)
CS DATA
Chip select input Serial data input
4 (5)
PCL
Power-on clear
5 (6) 6 (7) 7 (8) 8 (9)
VDD CKOUT OSCOUT OSCIN
Power supply Clock output LC oscillator input/ output OSCIN: External clock input
10 (11) 11 (14)
GND BLK1
Ground pin Blanking signal output 1
12 (15)
VC1
Character signal output 1
13 (16)
BLK2 (RBLK)
Blanking signal output 2 (blanking R)
14 (17)
VC2 (GBLK)
Character signal output 2 (blanking G) Blanking signal output (blanking B)
15 (18)
VBLK (BBLK)
16 (19) 17 (20) 18 (21) 19 (23)
VR VG VB Vsync
Character signal output
Vertical synchronizing signal input Horizontal synchronizing signal input No connection
Input a low-active vertical synchronizing signal to this pin.
20 (24)
Hsync
Input a low-active horizontal synchronizing signal to this pin.
(3, 12, 13, 22)
N.C.
Vacant pin
Notes 1. Pin numbers indicated in ( 2. Signals in (
) are that of the PD6461GT-xxx.
) are set by a mask option (RGB + RGB compatible blanking).
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PD6461, 6462
CONTENTS 1. MASK CODE OPTIONS ........................................................................................................................... 8
1.1 1.2 1.3 1.4 MASK CODE OPTIONS .................................................................................................................................. HOW TO SELECT MASK OPTIONS ............................................................................................................. 8 9
APPLICATION BLOCK DIAGRAMS .............................................................................................................. 10 DISPLAY IN RGB+VC1+VC2 MODE ................................................................................................................ 11 1.4.1 1.4.2 1.4.3 1.4.4 Character Signal Output When Option A is Selected .................................................................. 14 Character Signal Output When Option B is Selected .................................................................. 15 Character Signal Output When Option C is Selected .................................................................. 16 Display of VC2-Specified Characters ............................................................................................... 17
1.5
OUTPUTTING BACKGROUND ...................................................................................................................... 18
2.
COMMANDS ............................................................................................................................................. 19
2.1 2.2 2.3 COMMAND FORMAT ..................................................................................................................................... 19 COMMANDS AND THEIR BITS ..................................................................................................................... 19 POWER-ON CLEAR FUNCTION ................................................................................................................... 21
3.
COMMAND DETAILS ............................................................................................................................... 22
3.1 3.2 3.3 3.4 3.5 3.6 3.7 3.8 3.9 3.10 3.11 3.12 VIDEO RAM BATCH CLEAR COMMAND .................................................................................................... 22 CHARACTER DISPLAY CONTROL COMMAND .......................................................................................... 23 BACKGROUND/RIM COLOR CONTROL COMMAND ................................................................................. 24 3-CHANNEL INDEPENDENT DISPLAY ON/OFF COMMAND .................................................................... 25 CHARACTER REVERSE ON/OFF COMMAND ............................................................................................ 26 CHARACTER DISPLAY POSITION CONTROL COMMAND ....................................................................... 28 WRITE ADDRESS CONTROL COMMAND ................................................................................................... 30 OUTPUT PIN CONTROL COMMAND ........................................................................................................... 31 CHARACTER SIZE CONTROL COMMAND ................................................................................................. 32 3-CHANNEL INDEPENDENT BACKGROUND CONTROL COMMAND ..................................................... 33 TEST MODE COMMAND ................................................................................................................................ 35 DISPLAYED CHARACTER CONTROL COMMAND .................................................................................... 35
4.
COMMAND TRANSFER .......................................................................................................................... 38
4.1 4.2 4.3 4.4 1-BYTE COMMANDS ...................................................................................................................................... 38 2-BYTE COMMANDS ...................................................................................................................................... 38 2-BYTE CONTINUOUS COMMAND .............................................................................................................. 38 CONTINUOUS INPUT OF COMMAND .......................................................................................................... 39 4.4.1 When End Code is Not Used ............................................................................................................. 39 4.4.2 When End Code is Used .................................................................................................................... 39
5. 6. 7. 8. 9.
CHARACTER PATTERNS ....................................................................................................................... 40 ELECTRICAL CHARACTERISTICS ....................................................................................................... 50 APPLICATION CIRCUIT EXAMPLE ....................................................................................................... 54 PACKAGE DRAWINGS ........................................................................................................................... 55 RECOMMENDED SOLDERING CONDITIONS .................................................................................... 57 7
PD6461, 6462
1. MASK CODE OPTIONS
1.1 MASK CODE OPTIONS The PD6461, PD6462 provide mask options for selecting the following items:
Item (1) (2) (3) (4) (5) Data transfer Vertical display start position Pin selection Output distribution format Dot clock LSB first Specified in three-line units RGB+VC1+VC2 Option A LC oscillation Option B Selections MSB first Specified in nine-line units RGB+3BLK Option C External clock input
(1)
Data transfer Select the command transfer format.
(2)
Vertical display start position Select the units used for specifying the vertical display start position of the character display area. In three-line units, the vertical display start position can be set more finely than in nine-line units.
(3)
Pin selection Select the pins used to output character signals. In RGB+VC1+VC2 mode, character signals are output from the VR, VG, VB, VBLK, VC1, BLK1, VC2, and BLK2 pins. In RGB+3BLK mode, character signals are output from the VR, VG, VB, RBLK, GBLK, BBLK, VC1, and BLK1 pins. When displaying colored characters in a color viewfinder, select RGB+VC1+VC2 mode. When assigning a separate character signal for each color, select RGB+3BLK mode.
(4)
Output distribution format Select the format to be used to distribute character signals to the VC1 and VC2 channels when RGB+VC1+VC2 mode is selected. (When RGB+3BLK mode is selected, select option A as the output distribution format. Options B and C are invalid.) When an on-screen IC is used in a camcorder, some information is displayed in the viewfinder and recorded onto video tape (such as a date and title). Other information, however, need only be displayed in the viewfinder (battery or focus alarm and tape count). The PD6461, 6462 can distribute such information to different output channels in units of rows or half rows. You can select option A, option B, and option C as the output distribution format (only when RGB+VC1+VC2 mode is selected).
(5)
Dot clock Select the dot clock to be used to display characters. When an external clock input is selected, refer to EXTERNAL CLOCK INPUT in 6. ELECTRICAL CHARACTERISTICS.
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PD6461, 6462
1.2 HOW TO SELECT MASK OPTIONS To select mask options, use the option setting command (OC) of the Character Pattern Editor, a tool designed for editing character pattern data. Activate the Character Pattern Editor, then display the following setting menu: OC (COMMAND INPUT) OPTION DATA (0---LSB FAST , 1---MSB FAST OPTION DATA (0---V:9H , 1---V:3H ): ): ): ): ): ): ......... (1) ......... (2) ......... (3) ......... (4) ......... (5) ......... (6) ......... (7)
OPTION DATA (0---RGB+3BLK , 1---RGB+VC1+VC2 ) : OPTION DATA (0---OUTPUT 20 , 1---OUTPUT 21 OPTION DATA (0---OUTPUT 10 , 1---OUTPUT 11 OPTION DATA (0---EXT CLK OPTION DATA (0---LC , 1---LC , 1---EXT CLK
Actually, the above menu is displayed one line at a time. Once you have selected an option, the next line is displayed. Select 0 or 1 for lines (1), (2), (3), (6), and (7), according to the setting to be made. For the dot clock, however, make the same settings (different values) for lines (6) and (7). For example, when selecting LC oscillation, select "LC" for both lines (1 for (6) and 0 for (7)). Don't select external clock input for lines (6) and/or (7). When selecting the output distribution format, select the values on lines (4) and (5) as follows:
(4) Option A Option B Option C 1(OUTPUT 21) 0(OUTPUT 20) 1(OUTPUT 21) (5) 0(OUTPUT 10) 0(OUTPUT 10) 1(OUTPUT 11)
The settings are valid only when RGB+VC1+VC2 mode has been selected. Select option A (1, 0) when RGB+3BLK mode has been selected. The following table lists the correspondence between the command bits and the lines of the setting menu. Specify 0 or 1 for each bit.
D7 0 D6 (1) D5 (2) D4 (3) D3 (4) D2 (5) D1 (6) D0 (7)
Command OD displays the result of the selection, as a hexadecimal number. Example: When the mask options are selected as follows:
Mask option MSB first Specification in three-line units RGB+3BLK Option A (only option A can be specified in RGB+3BLK mode) LC oscillation Bit D6 D5 D4 D3 D2 D1 D0 Command 1 1 0 1 0 1 0
The command bits are set as follows:
D7 0 D6 1 D5 1 D4 0 D3 1 D2 0 D1 1 D0 0
Command OD displays 6AH.
9
PD6461, 6462
1.3 APPLICATION BLOCK DIAGRAMS Example of application to a camcorder (1) (in RGB+VC1+VC2 mode) (The VR, VG, VB, VBLK, VC1, BLK1, VC2, and BLK2 pins are used.)
Microcontroller
DATA CLK CS PCL
Hsync Vsync
RGB channel Image
Character addition circuit
Color viewfinder
PD6461, 6462
VC2 channel Character addition circuit Image + characters Recording system (deck)
VC1 channel
Character addition circuit
Monitor terminal (video signal output)
RGB channel: VR, VG, VB, VBLK
VC1 channel: VC1, BLK1 VC2 channel: VC2, BLK2
Example of application to a camcorder (2) (in RGB+3BLK mode for RGB compatible blanking) (The VR, VG, VB, RBLK, GBLK, and BBLK pins are used.)
Microcontroller
DATA CLK CS PCL
Hsync Vsync
R channel Image
Character addition circuit
Color viewfinder
PD6461, 6462
G channel Character addition circuit Image + characters Recording system (deck)
B channel
Character addition circuit
Monitor terminal (video signal output)
R channel: VR, RBLK
G channel: VG, GBLK
B channel: VB, BBLK
10
PD6461, 6462
1.4 DISPLAY IN RGB+VC1+VC2 MODE The PD6461, 6462 provide three options, A, B, and C, for the output distribution format. This section describes how character signals are output when each option is selected. Output is controlled with the output pin control command (refer to 3.8 OUTPUT PIN CONTROL COMMAND for details). Output pin control command for MSB-first transfer (Command bits are input starting from the most significant bit (MSB), D15.) (This command is a 2-byte command. 16 bits must be input for each command, even for continuous input.)
(MSB) D15 1 (LSB) D0 AR0
D14 0
D13 0
D12 1
D11 1
D10 1
D9 0
D8 0
D7 VC2
D6 VC1
D5 0
D4 0
D3 AR3
D2 AR2
D1 AR1
Row specification bits AR3 0 0 1 AR2 0 0 0 AR1 0 0 1 AR0 0 1 1 Function Specifies row 0. Specifies row 1. Specifies row 11.
Other values are invalid. Option A VC2 0 0 Option B VC2 0 0 Option C VC2 0 0 1 1 VC1 0 1 0 1 VC1 0 1 VC1 0 1 Output pin control bits Output from each pin VC1: Outputs a specified row. VC2: Fixed to low level. VC1: Fixed to low level. VC2: Outputs a specified row. Output pin control bits Output from each pin VC1: Outputs all rows. VC2: Fixed to low level. VC1: Outputs all rows. VC2: Outputs a specified row. Output pin control bits Output from each pin VC1: Outputs columns 0 to 23. VC2: Fixed to low level. VC1: Outputs columns 0 to 11. VC2: Outputs columns 12 to 23. VC1: Outputs columns 12 to 23. VC2: Outputs columns 0 to 11. VC1: Fixed to low level. VC2: Outputs columns 0 to 23.
* Row specification You can specify whether the VC1 or VC2 pin is used to output the character signals for each row (or each 12 columns). * Output pin control The signals output from the VC1 and VC2 pins depend on whether option A, B, or C is selected (the corresponding blanking signals are output in the same way).
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PD6461, 6462
Option A output
Output pin control bits VC2 0 0 VC1 0 1 Output from each pin VC1: Outputs the specified row. VC2: Fixed to low level. VC1: Fixed to low level. VC2: Outputs specified row. (1) (2)
Output channel For case (1) above VC1 channel
Character signal Outputs the logical OR of the character signals at the VR, VG, and VB pins (for the specified rows), excluding those characters for which the VC2 channel has been specified. Fixed to low level (for the specified rows)
Background signal (if specified) Outputs a background signal for areas other than those for which the VC2 channel has been specified.
VC2 channel
Outputs a background signal for those the areas for which the VC2 channel has been specified. Outputs a background signal for areas other than those for which the VC2 channel has been specified. Outputs a background signal for those the areas for which the VC2 channel has been specified.
For case (2) above
VC1 channel
Fixed to low level (for the specified rows)
VC2 channel
Outputs those characters for which the VC2 channel has been specified (for the specified rows).
Option B output
Output pin control bits VC2 0 0 VC1 0 1 Output from each pin VC1: Outputs all rows. VC2: Fixed to low level. VC1: Outputs all rows. VC2: Outputs a specified row. (1) (2)
Output channel For case (1) above VC1 channel
Character signal Outputs the logical OR of the character signals at the VR, VG, and VB pins (for all rows), excluding those characters for which the VC2 channel has been specified. Fixed to low level (for the specified rows)
Background signal (if specified) Outputs a background signal for areas other than those for which the VC2 channel has been specified.
VC2 channel
Outputs a background signal for those areas for which the VC2 channel has been specified. Outputs a background signal for areas other than those for which the VC2 channel has been specified.
For case (2) above
VC1 channel
Outputs the logical OR of the character signals at the VR, VG, and VB pins (for all rows), excluding those characters for which the VC2 channel has been specified. Outputs the characters for which the VC2 channel is specified (for the specified rows).
VC2 channel
Outputs a background signal for those areas for which the VC2 channel has been specified.
12
PD6461, 6462
Option C output
Output pin control bits VC2 0 0 1 1 VC1 0 1 0 1 Output from each pin VC1: Outputs columns 0 to 23. VC2: Fixed to low level. VC1: Outputs columns 0 to 11. VC2: Outputs columns 12 to 23. VC1: Outputs columns 12 to 23. VC2: Outputs columns 0 to 11. VC1: Fixed to low level. VC2: Outputs columns 0 to 23. (1) (2) (3) (4)
Output channel For case (1) above VC1 channel
Character signal Outputs the logical OR of the character signals at the VR, VG, and VB pins (for columns 0 to 23 in the specified rows), excluding those characters for which the VC2 channel has specified.
Background signal (if specified) Outputs a background signal for areas other than those for which the VC2 channel has been specified.
VC2 channel
Fixed to low level (for the specified rows)
Outputs a background signal for those areas for which the VC2 channel has been specified. Outputs a background signal for areas other than those for which the VC2 channel has been specified.
For case (2) above
VC1 channel
Outputs the logical OR of the character signals at the VR, VG, and VB pins (for columns 0 to 11 of the specified rows), excluding those characters for which the VC2 channel has been specified. Outputs the characters for which the VC2 channel has been specified (for columns 12 to 23 of the specified rows). Outputs the logical OR of the character signals at the VR, VG, and VB pins (for columns 12 to 23 of the specified rows), excluding those characters for which the VC2 channel has been specified. Outputs the characters for which the VC2 channel has been specified (for columns 0 to 11 of the specified rows). Fixed to low level (for the specified rows)
VC2 channel
Outputs a background signal for those areas for which the VC2 channel has been specified.
For case (3) above
VC1 channel
Outputs a background signal for areas other than those for which the VC2 channel has been specified.
VC2 channel
Outputs a background signal for those areas for which the VC2 channel has been specified.
For case (4) above
VC1 channel
Outputs a background signal for areas other than those for which the VC2 channel has been specified. Outputs a background signal for those areas for which the VC2 channel has been specified.
VC2 channel
Outputs the characters for which the VC2 channel has been specified (for columns 0 to 23 in the specified rows).
The RGB and VC1 channels do not output character signals for characters for which the VC2 channel has been specified. Background signals are output separately as listed above. In addition, the PD6461, 6462, when set to RGB+VC1+VC2 mode, provide the following output control: * Independent on/off control of character display for each channel (3-channel independent display on/off command) * Independent control of the background for each channel (3-channel independent background control command)
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PD6461, 6462
1.4.1 Character Signal Output When Option A is Selected Option A The VC1 bit of the output pin control command can be used to specify whether the characters of each row are output to the VC1 channel. Each character can be specified to be output to the VC2 channel, and the VC1 channel outputs only characters for which the VC2 channel in the rows for which the VC1 bit is set to 1. Characters for which the VC2 channel is specified are not output to the RGB or VC1 channel. Display example (when the VC2 channel is used for information to be recorded)
Display in viewfinder (RGB output and VC2 output)
REC
TAPE BATT 1/1000 YOKOHAMA BAY BRIDGE
Information that is only to be displayed, such as alarms and tape count
0000 AM 11:30 1991. 2.22 Information that is also to be recorded onto the video tape, such as the date and title
Output example with mask code option A specified
Characters output via RGB channel (colored characters) REC TAPE BATT 1/1000 Characters output via VC1 channel (specified rows) REC TAPE BATT 1/1000 YOKOHAMA BAY BRIDGE Characters output via VC2 channel (specified characters of specified rows)
0000
0000 AM 11:30 1991. 2.22
* The RGB channel does not output the characters for which the VC2 channel has been specified.
* The VC1 channel outputs the characters in the rows for which the VC1 bit is set to 0, excluding the characters for which the VC2 channel is specified. * Rows for which the VC1 bit is set to 1 are not output (the VC1 pin is fixed to low level).
* Rows for which the VC1 bit is set to 0 are not output (the VC2 pin is fixed to low level). * The VC2 channel outputs only those characters for which the VC2 channel has been specified in the rows for which the VC1 bit is set to 1.
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PD6461, 6462
1.4.2 Character Signal Output When Option B is Selected Option B The VC1 channel outputs characters of all rows regardless of setting of the VC1 and VC2 bits. Each character can be specified to be output to the VC2 channel, and the VC2 channel outputs only characters for which the VC2 channel in the rows for which the VC1 bit is set to 1. Characters for which the VC2 channel is specified are not output to the RGB or VC1 channel. Display example (when the VC2 channel is used for information to be recorded)
Display in viewfinder (RGB output and VC2 output) REC RAIN YOKOHAMA BAY BRIDGE TAPE BATT 1/1000 Information that is only to be displayed, such as alarms and tape count Information that is also to be recorded onto the video tape is displayed on the left (weather in this example).
0000 AM 11:30 1991. 2.22 Information that is also to be recorded onto the video tape, such as the date and title
Output example with mask code option B specified
Characters output via RGB channel (colored characters) REC TAPE BATT 1/1000 Characters output via VC1 channel (all rows) REC TAPE BATT 1/1000 Characters output via VC2 channel (specified characters of specified rows)
RAIN YOKOHAMA BAY BRIDGE
0000
0000 AM 11:30 1991. 2.22
* The RGB channel does not output the characters for which the VC2 channel has been specified.
* The VC1 channel outputs the characters of all rows regardless of the setting of the VC1 bit, excluding the characters for which the VC2 channel is specified.
* The VC2 channel outputs only those characters for which the VC2 channel has been specified in those rows for which the VC1 bit has been set to 1. * The VC2 channel outputs no characters in those rows for which the VC1 bit has been set to 0.
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PD6461, 6462
1.4.3 Character Signal Output When Option C is Selected Option C The VC1 and VC2 bits of the output pin control command can be used to specify whether the characters in columns 0 to 11 of each row and those in columns 12 to 23 are output to the VC1 channel or to the VC2 channel. Display example
Display in viewfinder 0 11 12 23 TAPE BATT 1/1000 YOKOHAMA BAY BRIDGE Information that is only to be displayed, such as alarms and tape count
0000 REC
AM 11:30 1991. 2.22
Information that is also to be recorded onto the video tape, such as date and title
Output example with mask code option C specified
Characters output via RGB channel (colored characters) TAPE BATT 1/1000 Characters output via VC1 channel (specified rows) TAPE BATT 1/1000 YOKOHAMA BAY BRIDGE Characters output via VC2 channel (specified characters)
0000 REC * The RGB channel does not output the characters for which the VC2 channel has been specified.
0000 REC * In the case of setting VC2 bit to 0, the VC1 channel outputs the characters of columns 0 to 23 in specified rows for which the VC1 bit is set to 0, or the characters of columns 0 to 11 in specified rows for which the VC1 bit is set to 1, excluding the characters for which the VC2 channel specified. * In the case of setting VC2 bit to 1, the VC1 channel outputs the characters of columns 12 to 23 in specified rows for which the VC1 bit is set to 0, and the rows for which the VC1 bit is set to 1 are not output (the VC1 pin is fixed to low level), excluding the characters for which the VC2 channel specified.
AM 11:30 1991. 2.22 * In the case of setting VC1 bit to 0, the VC2 channel outputs the characters of columns 0 to 11 in specified rows for which the VC2 bit is set to 1, and the rows for which the VC2 bit is set to 0 are not output (the VC2 pin is fixed to low level). * In the case of setting VC1 bit to 1, the VC2 channel outputs the characters of columns 12 to 23 in specified rows for which the VC2 bit is set to 0, or the characters of columns 0 to 23 in specified rows for which the VC2 bit is set to 1.
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PD6461, 6462
1.4.4 Display of VC2-Specified Characters When the displayed character control command specifies the VC2 channel for a character, that character is not output to the RGB or VC1 channel (display for the RGB and VC1 channels is usually the same as when display-off data is writtenNote). If background display (overall/minimum) is specified for the RGB or VC1 channel, no background is displayed for those characters for which the VC2 channel has been specified. Note In some cases, the display will differ slightly from the display-off data. Solid data: Character for which all 12 x 18 dots are filled
Solid data Displayoff data Solid data
* When display-off data is displayed for the RGB, VC1, or VC2 channel If a character adjacent to the display-off data is rimmed or has a background, the rim or background encroaches into the area for the displayoff data by one dot (minimum size). (The rim encroaches only at the filled dots at the left or right edge of the rimmed character.)
Solid data
VC2-specified character area
Solid data
* Display of VC2-specified character area for the RGB or VC1 channel If a character adjacent to a VC2-specified character is rimmed, the rim encroaches into the area for the VC2-specified character by one dot (minimum size). If the adjacent character has a background, however, the background does not encroach into the VC2-specified character area. * Display of VC2-specified character area for the VC2 channel If a rimmed VC2-specified character is adjacent to another VC2-specified character, the rim encroaches into the area for the latter VC2-specified character. The background does not encroach into the adjacent area (The rim encroaches only at the filled dots on the left or right edge of the rimmed character). * When a VC2-specified character area exists at the right or left edge of the entire display area
VC2-specified charac- (1) ter area
(The figure shows an area at the left edge. The case of an area at the
Solid data
right edge is similar). Encroachment of rim or background
(2)
Solid (3) data
Displayoff (4) data
Solid data
(with a width of one dot for the minimum character size)
Displayoff (5) data
Solid data
Encroachment of rim (1) - (5)
Encroachment of background (2) - (5)
Background does not encroach into the VC2-specified character area.
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PD6461, 6462
1.5 OUTPUTTING BACKGROUND The figures below show the screen display when minimum background or overall background is specified for each output channel in RGB+VC1+VC2 mode. (1) Minimum background
RGB channel VC1 output (character signal) VBLK1 output (background signal) F ABCD YOKOHAMA 1991. 9. 2 AM 10:00 F VC2 output (character signal) VBLK2 output (background signal) E 012345
ABCD YOKOHAMA 1991. 9. 2 AM 10:00
0000
No background for VC2-specified areas
No background for VC2-specified areas
Background only for VC2-specified areas
(2) Overall background
RGB channel VC1 output (character signal) VBLK1 output (background signal) F ABCD YOKOHAMA 1991. 9. 2 AM 10:00 F VC2 output (character signal) VBLK2 output (background signal) E 012345
ABCD YOKOHAMA 1991. 9. 2 AM 10:00
0000
No background for VC2-specified areas
No background for VC2-specified areas
Background only for VC2-specified areas
Remarks 1. The above figures are only examples. Actually, the background can be controlled independently for each output channel (only in RGB+VC1+VC2 mode), for example, by applying background (overall/minimum) for the RGB channel but not for the other channels. 2. No background is applied to the VC2-specified areas for the RGB or VC1 channel. If a character adjacent to a VC2-specified character is rimmed, the rim encroaches into the area for the VC2-specified character by one dot (minimum size) only at the filled dots at the left or right edge of the area of the rimmed character, in the same way as for display-off data. The background, however, does not encroach into the adjacent area.
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PD6461, 6462
2. COMMANDS
2.1 COMMAND FORMAT Control commands are serially input in 8-bit units with a variable word length. There are three types of commands: 1byte commands consisting of eight bits including an instruction and data, 2-byte commands consisting of sixteen bits including an instruction and data, and a 2-byte continuous command which can be input in an abbreviated format. Commands are input with the MSB first or LSB first according to the specified mask option. 2.2 COMMANDS AND THEIR BITS (1) For MSB first 1-byte commands
Function Video RAM batch clear Character display control Background/rim color control 3-channel independent display on/off Character reverse on/off (MSB) D7 0 0 0 0 0 D6 0 0 0 1 0 D5 0 0 1 1 1 D4 0 1 0 1 1 D3 0 D0 R 0 1 D2 0 LC G DOA 0 D1 0 BL1 B DOB 0 D0 0 BL0 BFC DOC BCRE
2-byte commands
Function Character display position control Write address control Output pin control Character size control 3-channel independent background control Test modeNote
(MSB) D15 D14 D13 D12 D11 D10 D9 1 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 0 1 1 1 0 0 0 0 1 0 0 0 V4 0 0 0 1 0 D8 V3 D7 V2 D6 V1 D5 V0 D4 H4 D3 H3 D2 H2 D1 H1 D0 H0
AR3 AR2 AR1 AR0 AC4 AC3 AC2 AC1 AC0 0 0 VC2 0 VC1 S 0 0 0 0 AR3 AR2 AR1 AR0 AR3 AR2 AR1 AR0
BA1 BA0 BFA BB1 BB0 BFB BC1 BC0 BFC T8 T7 T6 T5 T4 T3 T2 T1 T0
Note Not to be used 2-byte continuous command
(MSB) Function Displayed character control D15 D14 D13 D12 D11 D10 D9 1 1 RV R G B BL D8 VC2 D7 C7
Note
D6 C6
D5 C5
D4 C4
D3 C3
D2 C2
D1 C1
D0 C0
Note C7 bit is "don't care" at the PD6462. However, this data sheet explains the PD6462 with "0" in the C7 bit.
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(2) For LSB first 1-byte commands
Function Video RAM batch clear Character display control Background/rim color control 3-channel independent display on/off Character reverse on/off (LSB) D0 0 BL0 BFC DOC BCRE D1 0 BL1 B DOB 0 D2 0 LC G DOA 0 D3 0 DO R 0 1 D4 0 1 0 1 1 D5 0 0 1 1 1 D6 0 0 0 1 0 D7 0 0 0 0 0
2-byte commands
Function Character display position control Write address control Output pin control Character size control 3-channel independent background control Test modeNote
(LSB) D0 V3 AR3 0 0 BA1 T8 D1 V4 0 0 0 1 0 D2 0 0 1 0 0 0 D3 0 1 1 1 0 0 D4 0 0 1 1 1 1 D5 0 0 0 0 1 1 D6 0 0 0 0 0 0 D7 1 1 1 1 1 1 D8 H0 D9 D10 D11 D12 D13 D14 D15 H1 H2 H3 H4 V0 V1 V2
AC0 AC1 AC2 AC3 AR4 AR0 AR1 AR2 AR0 AR1 AR2 AR3 AR0 AR1 AR2 AR3 0 0 0 0 VC1 S VC2 0
BFC BC0 BC1 BFB BB0 BB1 BFA BA0 T0 T1 T2 T3 T4 T5 T6 T7
Note Not to be used 2-byte continuous command
Function Displayed character control
(LSB) D0 VC2 D1 BL D2 B D3 G D4 R D5 RV D6 1 D7 1 D8 C0 D9 D10 D11 D12 D13 D14 D15 C1 C2 C3 C4 C5 C6 C7
Note
Note C7 bit is "don't care" at the PD6462. However, this data sheet explains the PD6462 with "0" in the C7 bit.
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PD6461, 6462
2.3 POWER-ON CLEAR FUNCTION The internal state of the IC is unstable immediately after the power is turned on. It is therefore necessary to keep the PCL pin low for the time shown below to allow the system to initialize. This power-on clear places the system in the following state: * Test mode is not specified. * All character data in video RAM (12 rows x 24 columns) is cleared (to display-off data (FEH: PD6461/7EH: PD6462)) and blinking is turned off. * The video RAM write address is (row 0, column 0). * The character size is single (minimum) for all rows. * The output distribution format is set to the default (the VC1 and VC2 bits are set to 0). * Display is turned off and LC oscillation is turned on. The time required for power-on clear is calculated as follows. No commands must be input during this time.
Time required for power-on clear = tPCLLNote + {Time required for clearing video RAM} = 10(s) + {10(s) + 12/fOSC(MHz) x 288} fOSC(MHz) : LC oscillation frequency or external clock frequency Note Refer to POWER-ON CLEAR SPECIFICATIONS in 6. ELECTRICAL CHARACTERISTICS.
A dot clock input (to the OSCIN pin) is necessary to clear video RAM. Input a dot clock when an external clock input is selected.
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3. COMMAND DETAILS
3.1 VIDEO RAM BATCH CLEAR COMMAND This command clears the entire video RAM by means of a single operation (the bit configuration is the same as for MSBfirst and LSB-first transfer).
(MSB) D7 0 D6 0 D5 0 D4 0 D3 0 D2 0 D1 0 (LSB) D0 0
The video RAM batch clear command places the system in the following state: * All character data in video RAM (12 rows x 24 columns) is cleared (to display-off data (FEH: PD6461/7EH:
PD6462)) and blinking is turned off.
* The video RAM write address is (row 0, column 0). * The character size is single (minimum) for all rows. * The output distribution format is set to the default (the VC1 and VC2 bits are set to 0). * Display is turned off and LC oscillation is turned on. The time required for clearing video RAM is calculated as follows. No command must be input while the video RAM is being cleared.
Time required to clear video RAM = 10(s) + 12/fOSC(MHz) x 288 fOSC(MHz) : LC oscillation frequency or external clock frequency
A dot clock input (to the OSCIN pin) is necessary to clear the video RAM. Input a dot clock when external clock input is selected. Remark Power-on clear using the PCL pin is hardware reset, initializing the IC, including clearing the video RAM and releasing test mode. The video RAM batch clear command, in contrast, performs software reset by initializing the IC without first releasing test mode.
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PD6461, 6462
3.2 CHARACTER DISPLAY CONTROL COMMAND This command turns on/off character display, LC oscillation, and the blinking of characters. (1) For MSB-first transfer (Command bits are input starting from the MSB (D7).)
(MSB) D7 0 D6 0 D5 0 D4 1 D3 DO D2 LC D1 BL1 (LSB) D0 BL0
BL1 0 0 1 1
Blinking control bits BL0 Function 0 Turns off blinking. 1 Turns on 2 Hz blinking. 0 Turns on 1 Hz blinking. 1 Turns on 0.5 Hz blinking. LC oscillation control bit Function Turns off LC oscillator. Turns on LC oscillator. Character display on/off control bit Function Turns off character display. Turns on character display.
LC 0 1
DO 0 1
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as that for MSB-first transfer.)
(LSB) D0 BL0 D1 BL1 D2 LC D3 DO D4 1 D5 0 D6 0 (MSB) D7 0
* Blinking control bits These bits are used to turn on or off the blinking of characters for which blinking has been enabled with the displayed character control command. The blinking ratio is 1:1, one of three blinking frequencies being selectable for the entire screen. * LC oscillation control bit This bit is used to turn the oscillator on or off. You can stop the oscillator when no character is being displayed, thus reducing the power consumption. While the oscillator is stopped, it is not possible to write to video RAM. Turn on the oscillator before attempting to write to video RAM. Cautions 1. When using LC oscillation (LC oscillation control bit = 1): When character display is turned on, the oscillation is synchronized with Hsync, stopping when Hsync goes low. When character display is turned off, oscillation continues regardless of the state of Hsync. 2. When using an external clock (LC oscillation control bit = 1): While the oscillator is turned on, clock pulses are supplied to the IC internal circuit. While the oscillator is turned off, no clock pulses are supplied.
* Character display on/off control bit This bit is used to turn character display on or off. Character display is turned on or off upon the detection of a falling edge of Hsync.
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PD6461, 6462
3.3 BACKGROUND/RIM COLOR CONTROL COMMAND This command specifies the color of the background or rim when overall background, minimum background, or rimming is specified. (1) For MSB-first transfer (Command bits are input starting from the MSB (D7).)
(MSB) D7 0 D6 0 D5 1 D4 0 D3 R D2 G D1 B (LSB) D0 BFC BFC 0 1 Rim color specification bit Color Black White
R 0 0 0 0 1 1 1 1
Background color specification bits Color G B Black 0 0 Blue 0 1 Green 1 0 Cyan 1 1 Red 0 0 Magenta 0 1 Yellow 1 0 White 1 1
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as that for MSB-first transfer.)
(LSB) D0 BFC D1 B D2 G D3 R D4 0 D5 1 D6 0 (MSB) D7 0
* Rim color specification bit This bit is used to specify the color (white or black) of the rim added to all characters displayed on the screen (only for the RGB channel). When rimming is specified for the VC1 or VC2 channel, the rim color is always black. * Background color specification bits These bits are used to specify one of eight colors to be used for the background of the entire screen (only for the RGB channel). When background (overall/minimum) is specified for the VC1 or VC2 channel, the background color is always black.
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PD6461, 6462
3.4 3-CHANNEL INDEPENDENT DISPLAY ON/OFF COMMAND This command turns character display on or off independently for each of the three channels. (1) For MSB-first transfer (Command bits are input starting from the MSB (D7).)
(MSB) D7 0 D6 1 D5 1 D4 1 D3 0 D2 DOA D1 DOB (LSB) D0 DOC
When RGB+VC1+VC2 mode is selected
Control bits 0 DOA 1 0 DOB 1 0 DOC 1 Control bits 0 DOA 1 DOB - DOC -
Function Turns off display for RGB channel. Turns on display for RGB channel. Turns off display for VC1 channel. Turns on display for VC1 channel. Turns off display for VC2 channel. Turns on display for VC2 channel. Function Turns off character display (for all channels). Turns on character display (for all channels). Don't care Don't care
When RGB+3BLK mode is selected
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as that for MSB-first transfer.)
(LSB) D0 DOC D1 DOB D2 DOA D3 0 D4 1 D5 1 D6 1 (MSB) D7 0
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PD6461, 6462
3.5 CHARACTER REVERSE ON/OFF COMMAND This command specifies whether all characters displayed on the screen are reversed. (1) For MSB-first transfer (Command bits are input starting from the MSB (D7).)
(MSB) D7 0 D6 0 D5 1 D4 1 D3 1 D2 0 D1 0 (LSB) D0 BCRE Control bit 0 BCRE 1 Function Does not reverse characters. Reverses characters.
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as that for MSB-first transfer.)
(LSB) D0 BCRE D1 0 D2 0 D3 1 D4 1 D5 1 D6 0 (MSB) D7 0
Each character is reversed only when reversing of the character is enabled with the displayed character control command. * Example of reversed character (uppercase letter "I")
When not reversed When reversed
Background color or image (where dots are not filled in the character pattern)
Character color when not reversed
Character color (where dots are filled in the character pattern)
Black
Remark When the character is not reversed, one of eight colors can be selected for the background color for the RGB channel. For the VC1 and VC2 channels, which can display only white or black, the background is always black (characters are white). When characters are rseversed for the VC1 or VC2 channel, the display is as follows: * Example of reversed character for VC1 or VC2 channel (uppercase letter "I")
When not reversed When reversed
Background color (black) or image (where dots are not filled in the character pattern)
Character color when not reversed: White
Character color: White (where dots are filled in the character pattern)
Black
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PD6461, 6462
* Rimming of reversed character For an ordinary character
When not reversed Image When reversed
Rim
Black No rim
Character color
Character color when not reversed
For a solid character (character pattern 18H (PD6461)/1FH (PD6462): Refer to 5. CHARACTER PATTERNS)
When not reversed When reversed
Rim
Black No rim
Character color
Display-off data does not change when reversed. When blank data is reversed, it becomes a solid character for which the character color is initially set. The character color can be set only for the RGB channel. It is always white (black when reversed) for the VC1 and VC2 channels.
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PD6461, 6462
3.6 CHARACTER DISPLAY POSITION CONTROL COMMAND This command specifies the character display start position with one of 32 steps in 12-dot units for the horizontal direction, and one of 32 steps in three-line units for the vertical direction (this command is a 2-byte command, requiring 16 bits for each command even when continuously input). (1) For MSB-first transfer (Command bits are input starting from the MSB (D15).)
(MSB) D15 1 D14 0 D13 0 D12 0 D11 0 D10 0 D9 V4 D8 V3 D7 V2 D6 V1 D5 V0 D4 H4 D3 H3 D2 H2 D1 H1 (LSB) D0 H0
H4 0 0
Control bits for horizontal display start position H3 H2 H1 H0 Start position 0 0 0 0 0 0 0 1 (4 + 12 x 1)/fOSC (MHz) from rising edge of Hsync (s) (4 + 12 x 2)/fOSC (MHz) from rising edge of Hsync (s)
1
1
1
1
1
(4 + 12 x 32 )/fOSC (MHz) from rising edge of Hsync (s)
Remarks fOSC: LC oscillation frequency or external input clock Control bits for vertical display start position V2 V1 V0 Start position 0 0 0 0 0 1 3H x 0 + 1H (9H x 0 + 1H) from rising edge of Vsync 3H x 1 + 1H (9H x 1 + 1H) from rising edge of Vsync
V4 0 0
V3 0 0
1
1
1
1
1
3H x 31 + 1H (9H x 31 + 1H) from rising edge of Vsync
Remarks 1. H: Line 2. ( ) shows when units of nine lines are selected by specifying a mask option.
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as that for MSB-first transfer.)
(LSB) D0 V3 D1 V4 D2 0 D3 0 D4 0 D5 0 D6 0 D7 1 D8 H0 D9 H1 D10 H2 D11 H3 D12 H4 D13 V0 D14 V1 (MSB) D15 V2
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PD6461, 6462
* Control bits for the horizontal display start position These bits are used to specify the horizontal display start position (timing) as one of 32 steps in units of 12 dots (12/fOSC (MHz)). Settable positions are based on the rising edge of the horizontal synchronizing signal input to the Hsync pin. The 32 positions are calculated by adding 12 dots, one to 32 times, to the position equivalent to 16 clock pulses (16/fOSC (MHz)) from the rising edge (fOSC (MHz): LC oscillation frequency or external input clock frequency). * Control bits for the vertical display start position These bits are used to specify the vertical display start position as one of 32 steps in units of three lines (or 32 steps in units of nine lines when specified with a mask option). The minimum settable position is three lines from a rising edge of the vertical synchronizing signal input to the Vsync pin.
Horizontal synchronizing signal (Hsync)
A
B
Display area of 12 rows x 24 columns
Vertical synchronizing signal (Vsync)
A : 3Hx(24V4+23V3+22V2+21V1+20V0)+1H 9H when units of nine lines are selected by specifying a mask option 12 4 B : x(24H4+23H3+22H2+21H1+20H0+1) + fOSC(MHz) fOSC(MHz) fOSC : LC oscillation frequency or external input clock frequency H : Line
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PD6461, 6462
3.7 WRITE ADDRESS CONTROL COMMAND This command specifies the address at which a character is written in the display area (video RAM) of 12 rows x 24 columns (this command is a 2-byte command, requiring 16 bits for each command, even when continuously input). (1) For MSB-first transfer (Command bits are input starting from the MSB (D15).)
(MSB) D15 1 D14 0 D13 0 D12 0 D11 1 D10 0 D9 0 D8 AR3 D7 AR2 D6 AR1 D5 AR0 D4 AC4 D3 AC3 D2 AC2 D1 AC1 (LSB) D0 AC0
Column address specification bits Column AC4 AC3 AC2 AC1 AC0 Column 0 0 0 0 0 0 Column 1 0 0 0 0 1 1 0 1 1 1 Any other value is invalid. Column 23
Column address specification bits Row address specification bits AR3 AR2 AR1 AR0 Row 0 0 0 0 Row 0 0 0 0 1 Row 1 Row 11 1 0 1 1 Any other value is invalid.
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as that for MSB-first transfer.)
(LSB) D0 AR3 D1 0 D2 0 D3 1 D4 0 D5 0 D6 0 D7 1 D8 AC0 D9 AC1 D10 AC2 D11 AC3 D12 AR4 D13 AR0 D14 AR1 (MSB) D15 AR2
* Column write address specification bits The display area has 24 columns. These bits are used to specify the column in which a character is to be written. * Row write address specification bits The display area has 12 rows. These bits are used to specify the row in which a character is to be written.
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PD6461, 6462
3.8 OUTPUT PIN CONTROL COMMAND This command distributes character signals to the VC1 and VC2 channels (this command is a 2-byte command, requiring 16 bits for each command, even when continuously input). The PD6461, 6462 support a mask option for selecting one of three formats for the output distribution format for the VC1 and VC2 channels. (1) For MSB-first transfer (Command bits are input starting from the MSB (D15).)
(MSB) D15 1 D14 0 D13 0 D12 1 D11 1 D10 1 D9 0 D8 0 D7 VC2 D6 VC1 D5 0 D4 0 D3 AR3 D2 AR2 D1 AR1 (LSB) D0 AR0
Row specification bits AR3 0 0 1 AR2 0 0 0 AR1 0 0 1 AR0 0 1 1 Function Specifies row 0. Specifies row 1. Specifies row 11.
Other values are invalid. Option A VC2 0 0 Option B VC2 0 0 Option C VC2 0 0 1 1 VC1 0 1 0 1 VC1 0 1 VC1 0 1 Output pin control bits Output from each pin VC1: Outputs a specified row. VC2: Fixed to low level. VC1: Fixed to low level. VC2: Outputs a specified row. Output pin control bits Output from each pin VC1: Outputs all rows. VC2: Fixed to low level. VC1: Outputs all rows. VC2: Outputs a specified row. Output pin control bits Output from each pin VC1: Outputs columns 0 to 23. VC2: Fixed to low level. VC1: Outputs columns 0 to 11. VC2: Outputs columns 12 to 23. VC1: Outputs columns 12 to 23. VC2: Outputs columns 0 to 11. VC1: Fixed to low level. VC2: Outputs columns 0 to 23.
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as that for MSB-first transfer.)
(LSB) D0 0 D1 0 D2 1 D3 1 D4 1 D5 0 D6 0 D7 1 D8 AR0 D9 AR1 D10 AR2 D11 AR3 D12 0 D13 0 D14 VC1 (MSB) D15 VC2
* Row specification bits Output distribution to the VC1 and VC2 pins is specified for each row (or for 12 columns). These bits are used to specify the row. * Output pin control bits These bits are used to distribute character output signals to the VC1 and VC2 pins depending on whether option A, B, or C has been selected by specifying a mask option (the corresponding blanking signals are output likewise).
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PD6461, 6462
3.9 CHARACTER SIZE CONTROL COMMAND This command specifies the character size (height and width at one time) for each row (this command is a 2-byte command, requiring 16 bits for each command, even when continuously input). (1) For MSB-first transfer (Command bits are input starting from the MSB (D15).)
(MSB) D15 1 D14 0 D13 0 D12 1 D11 1 D10 0 D9 0 D8 0 D7 0 D6 S D5 0 D4 0 D3 AR3 D2 AR2 D1 AR1 (LSB) D0 AR0
Row specification bits Row AR3 AR2 AR1 AR0 Row 0 0 0 0 0 Row 1 0 0 0 1 1 0 1 1 Any other value is invalid. 1 fOSC(MHz) (fOSC : LC oscillation frequency 1t (s) = Row 11
S 0 1
Character size specification bit Size Height: One dot per line. Width: One dot per 1t (minimum dot). Height: One dot per two lines. Width: One dot per 2t.
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as that for MSB-first transfer.)
(LSB) D0 0 D1 0 D2 0 D3 1 D4 1 D5 0 D6 0 D7 1 D8 AR0 D9 AR1 D10 AR2 D11 AR3 D12 0 D13 0 D14 S (MSB) D15 0
* Row specification bits The character size is specified for each row. These bits are used to specify the row. * Character size specification bit This bit is used to select either of two supported sizes.
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PD6461, 6462
3.10 3-CHANNEL INDEPENDENT BACKGROUND CONTROL COMMAND This command specifies the background for each of the three output channels (this command is a 2-byte command, requiring 16 bits for each command, even when continuously input). (1) For MSB-first transfer (Command bits are input starting from the MSB (D15).)
(MSB) D15 1 D14 0 D13 1 D12 1 D11 0 D10 0 D9 1 D8 BA1 D7 BA0 D6 BFA D5 BB1 D4 BB0 D3 BFB D2 BC1 D1 BC0 (LSB) D0 BFC
VC2 output
Background control bits for VC2 channel BC1 0 0 1 1 BC0 0 1 0 1 Background No background Minimum background Not to be set Overall background
Rimming control bit for VC2 channel BFC 0 1 VC1 output Function Does not rim characters. Rims characters.
Background control bits for VC1 channel BB1 0 0 1 1 BB0 0 1 0 1 Background No background Minimum background Not to be set Overall background
Rimming control bit for VC1 channel BFB 0 1 RGB output Function Does not rim characters. Rims characters.
Background control bits for RGB channel BA1 0 0 1 1 BA0 0 1 0 1 Background No background Minimum background Not to be set Overall background
Rimming control bit for RGB channel BFA 0 1 Function Does not rim characters. Rims characters.
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as that for MSB-first transfer.)
(LSB) D0 BA1 D1 1 D2 0 D3 0 D4 1 D5 1 D6 0 D7 1 D8 BFC D9 BC0 D10 BC1 D11 BFB D12 BB0 D13 BB1 D14 BFA (MSB) D15 BA0
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PD6461, 6462
* Rimming control bit This bit is used to specify whether all characters displayed on the screen are rimmed. Rimming: Whenever there is a dot at the right or left edge of the display area for a character, rimming of the dot will encroach into the adjacent character display area. For dots at the top or bottom edge, however, no rim is added either above the top edge or below the bottom edge, that is, rimming does not encroach into the character display area above or below. Other dots are rimmed as shown below. Example
Character dots Rim
The width of a rim is always 1t (minimum dot) regardless of the character size.
* Background control bits These bits are used to select no background, minimum background, or overall background as the background type. The background color is specified with the background/rim color control command. No background: Outputs only character data. of one dot at each side. Overall background: Adds a background over the entire screen.
Minimum background: Adds a background of an area that is wider than the character display area by a minimum
* Background and rimming in RGB+VC1+VC2 mode Characters for which the VC2 channel is specified with the displayed character control command are not output to the RGB or VC1 channel. When background (minimum/overall) is specified for the RGB or VC1 channel, no background is added to the areas for the VC2-specified characters. By contrast for the VC2 channel, a background is added only to those areas for VC2-specified characters. (Refer to 1.4 DISPLAY IN RGB+VC1+VC2 MODE and 1.4.4 Display of VC2-Specified Characters for details of the display of VC2-specified character areas for the RGB or VC1 channel.) When RGB+3BLK (RGB compatible blanking) mode is selected, only the background control bits for the RGB channel are valid. Those for the VC1 and VC2 channels are invalid (In RGB+3BLK mode, no pin outputs a signal for the VC2 channel. The VC1 pin is used to output the logical OR of the R, G, and B outputs.).
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PD6461, 6462
3.11 TEST MODE COMMAND This command is used only to test the IC. Usually, do not input this command. The system cannot enter test mode while the TEST pin (pin 9) is connected to ground. (1) For MSB-first transfer (Command bits are input starting from the MSB (D15).)
(MSB) D15 1 D14 0 D13 1 D12 1 D11 0 D10 0 D9 0 D8 T8 D7 T7 D6 T6 D5 T5 D4 T4 D3 T3 D2 T2 D1 T1 (LSB) D0 T0
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as that for MSB-first transfer.)
(LSB) D0 T8 D1 0 D2 0 D3 0 D4 1 D5 1 D6 0 D7 1 D8 T0 D9 T1 D10 T2 D11 T3 D12 T4 D13 T5 D14 T6 (MSB) D15 T7
3.12 DISPLAYED CHARACTER CONTROL COMMAND This command specifies the attributes of each character, including the character pattern, color, and whether it is blinked. When inputting this command, ensure that LC oscillator is turned on (if the LC oscillator is turned off, it is not possible to write to video RAM). This command is a 2-byte continuous command. When continuously writing characters with the same attributes (except for a pattern), you need input only the eight low-order bits (D0 to D7) of the command for the second and subsequent characters. In this case, the write column address is automatically incremented (After a character has been written into column 23, the next character is automatically written into left-most column 0 of the next row. When a character is written into column 23 of row 11, the next character is automatically written into column 0 of row 0.).
Column address ()
Row n
0 1 2 * * * * * * * * * * * * 21 22 23
Row address
()
Row address incremented
Row n+1
0 1 2 * * * * * * * * * * * * 21 22 23
35
PD6461, 6462
(1) For MSB-first transfer (Command bits are input starting from the MSB (D15).)
(MSB) D15 1 D14 1 D13 RV D12 R D11 G D10 B D9 BL D8 VC2 D7 C7Note D6 C6 D5 C5 D4 C4 D3 C3 D2 C2 D1 C1 (LSB) D0 C0
Character pattern specification bits C7
Note
C6 0 0
C5 0 0
C4 0 0
C3 0 0
C2 0 0
C1 0 0
C0 0 1
Function Outputs pattern at address 00H. Outputs pattern at address 01H. FEH (PD6461)/7EH (PD6462) (display-off data). FFH (PD6461)/7FH ( PD6462) (Indicates the end of second-byte continuous input.) VC2 channel specification bit VC2 0 1 Function Does not specify output to VC2 channel. Specifies output to VC2 channel. Blinking control bit BL 0 1 Function Disables blinking. Enables blinking.
0 0
1 1
1 1
1 1
1 1
1 1
1 1
1 1
0 1
Character color specification bits R 0 0 0 0 1 1 1 1 G 0 0 1 1 0 0 1 1 B 0 1 0 1 0 1 0 1 Color Black Blue Green Cyan Red Magenta Yellow White
Reversing control bit RV 0 1 Function Disables reversing. Enables reversing.
Note C7 bit is "don't care" at the PD6462. However, this data sheet explains the PD6462 with "0" in the C7 bit.
36
PD6461, 6462
(2) For LSB-first transfer (Command bits are input starting from the LSB (D0). The function of each bit is the same as that for MSB-first transfer.)
(LSB) D0 VC2 D1 BL D2 B D3 G D4 R D5 RV D6 1 D7 1 D8 C0 D9 C1 D10 C2 D11 C3 D12 C4 D13 C5 D14 C6 (MSB) D15 C7
* Character pattern specification bits These bits are used to specify the address of the character pattern to be used. Address FEH (PD6461)/7EH (PD6462) indicates display-off data and address FFH (PD6461)/7FH (PD6462) indicates the end code for secondbyte continuous input. The design of each character pattern can be modified by specifying a mask code option (except for addresses FEH and FFH (PD6461)/7EH and 7FH (PD6462)). * VC2 channel specification bit This bit is used to specify whether each character is output to the VC2 channel. Characters for which the VC2 channel is specified are not output to the RGB or VC1 channel (This bit is invalid in RGB+3BLK mode). * Blinking control bit This bit is used to enable or disable blinking for each character. Blinking of characters is turned on/off for the entire screen with the character display control command (refer to 3.2 CHARACTER DISPLAY CONTROL COMMAND). * Character color specification bits These bits are used to specify the color of each character (These bits are valid only for the RGB channel. Only a single color can be used for the VC1 and VC2 channels). * Reversing control bit This bit is used to enable or disable reversing for each character. The characters of the entire screen are reversed with the character reverse on/off command (refer to 3.5 CHARACTER REVERSE ON/OFF COMMAND).
37
PD6461, 6462
4. COMMAND TRANSFER
4.1 1-BYTE COMMANDS
MSB first: Input starting from bit D7 LSB first: Input starting from bit D0
DATA DATA CLK CS
D7 - D0 D0 - D7
4.2 2-BYTE COMMANDS
First byte DATA D15 - D8 First byte DATA CLK CS D0 - D7 Second byte D7 - D0 Second byte D8 - D15 MSB first First byte: D15 to D8 Second byte: D7 to D0 LSB first First byte: D0 to D7 Second byte: D8 to D15
When inputting a 2-byte command, keep the CS signal low between the first and second bytes of the command. 4.3 2-BYTE CONTINUOUS COMMAND
First byte DATA D15 - D8 First byte DATA D0 - D7 Second byte D7 - D0 Second byte D8 - D15 Second byte D7 - D0 Second byte D8 - D15 LSB first MSB first
CLK CS
The 2-byte continuous command is used to write characters to video RAM. When continuously writing characters for which the specifications for the color, blinking, reversing, and VC2 channel are the same, transfer the first byte of the first command then continuously transfer only the second bytes (character pattern addresses) of the commands. When changing any part of the first byte, end continuous input (by setting the CS signal to high or transferring the end code for second-byte continuous input) then transfer the newly modified first byte.
38
PD6461, 6462
4.4 CONTINUOUS INPUT OF COMMAND Transfer each of the 1-byte, 2-byte, and 2-byte successive commands from a microcontroller to the PD6461, 6462 as follows. To transfer a 1-byte or 2-byte command, or a 2-byte successive command with blinking data changed after a 2byte successive command has been transferred, either make CS high once, or transfer 2-byte successive command end code (FFH: PD6461/7FH: PD6462) at the end of the 2-byte successive command. In the latter case, it is not necessary to make CS high. 4.4.1 When End Code is Not Used Example 1-byte command 2-byte successive command 1-byte command
1-byte command 2-byte successive command 1st byte D15-D8 (D0-D7) 1-byte command 2nd byte D7-D0 (D8-D15) 00H-FEH ( PD6461) 00H-7EH ( PD6462) (normal character) 2nd byte D7-D0 (D8-D15) 00H-FEH (PD6461) 00H-7EH ( PD6462) (normal character) D7-D0 (D0-D7) MSB first (LSB first)
DATA
D7-D0 (D0-D7)
CLK
CS
Make CS low once and then back high again.
4.4.2 When End Code is Used Example 1-byte command 2-byte successive command 1-byte command
1-byte command 2-byte successive command 1st byte D15-D8 (D0-D7) 1-byte command 2nd byte D7-D0 (D8-D15) 00H-FEH ( PD6461) 00H-7EH ( PD6462) (normal character) 2nd byte D7-D0 (D8-D15) FFH ( PD6461)/ 7FH ( PD6462) (2-byte successive command end code) D7-D0 (D0-D7) MSB first (LSB first)
DATA
D7-D0 (D0-D7)
CLK
CS
It is not necessary to make CS low and then back high again.
Remark By using the 2-byte successive command end code, the CS pin may remain low. However, it is recommended to make CS pin high to improve the noise immunity.
39
PD6461, 6462
5. CHARACTER PATTERNS
The PD6461, 6462 can display 256 (PD6461)/128 (PD6462) character patterns, including alphanumerics, Kanji characters, and symbols, which are stored in the character generator ROM. Each pattern in the character generator ROM can be modified by specifying a mask code option. However, the display-off data at character address FEH (PD6461)/ 7EH (PD6462) and end code for second-byte continuous input at FFH (PD6461)/7FH (PD6462) cannot be modified. No character pattern can be stored at these addresses. When none of the 12 x 18 dots are filled for a character pattern at addresses 00H to FDH (PD6461)/00H to 7DH (PD6462), the character pattern is called blank data. Character address FEH (PD6461)/7EH (PD6462) contains displayoff data. Blank data and display-off data are represented in the same way (with no dots filled) in character patterns shown on the following pages, but they are different as follows: Table 5-1 The Differences between Blank Data and Display-off Data
Display of character area in each background mode Character data No background Blank data Display-off data Displays image. Displays image. Minimum background Displays background. Displays image only (without background). Overall background Displays background. Displays image only (without background).
You cannot specify display-off data for addresses other than FEH (PD6461)/7EH (PD6462) when using a mask code option. Blank data, however, can be specified at any address from 00H to FDH (PD6461)/00H to 7DH (PD6462) (address FFH (PD6461)/7FH (PD6462) cannot be used because it contains the end code for second-byte continuous input). The character patterns of the PD6461GS-101/102, PD6462GS-001 (NEC's standard model) are shown on the following pages.
40
PD6461, 6462
PD6461GS-101/102 Character Patterns
00H 01H 02H 03H 04H 05H 06H 07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
41
PD6461, 6462
30H 31H 32H 33H 34H 35H 36H 37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
42
PD6461, 6462
60H 61H 62H 63H 64H 65H 66H 67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EH
7FH
80H
81H
82H
83H
84H
85H
86H
87H
88H
89H
8AH
8BH
8CH
8DH
8EH
8FH
43
PD6461, 6462
90H 91H 92H 93H 94H 95H 96H 97H
98H
99H
9AH
9BH
9CH
9DH
9EH
9FH
A0H
A1H
A2H
A3H
A4H
A5H
A6H
A7H
A8H
A9H
AAH
ABH
ACH
ADH
AEH
AFH
B0H
B1H
B2H
B3H
B4H
B5H
B6H
B7H
B8H
B9H
BAH
BBH
BCH
BDH
BEH
BFH
44
PD6461, 6462
C0H C1H C2H C3H C4H C5H C6H C7H
C8H
C9H
CAH
CBH
CCH
CDH
CEH
CFH
D0H
D1H
D2H
D3H
D4H
D5H
D6H
D7H
D8H
D9H
DAH
DBH
DCH
DDH
DEH
DFH
E0H
E1H
E2H
E3H
E4H
E5H
E6H
E7H
E8H
E9H
EAH
EBH
ECH
EDH
EEH
EFH
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PD6461, 6462
F0H F1H F2H F3H F4H F5H F6H F7H
F8H
F9H
FAH
FBHNote 1
FCH
FDH
FEHNote 2
FFHNote 3
Notes 1. Blank data 2. Display-off data (fixed at this address) 3. End code for second-byte continuous input (fixed at this address)
46
PD6461, 6462
PD6462GS-001 Character Patterns
00H 01H 02H 03H 04H 05H 06H 07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10HNote 1
11H
12H
13H
14H
15H
16H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
2CH
2DH
2EH
2FH
47
PD6461, 6462
30H
31H
32H
33H
34H
35H
36H
37H
38H
39H
3AH
3BH
3CH
3DH
3EH
3FH
40H
41H
42H
43H
44H
45H
46H
47H
48H
49H
4AH
4BH
4CH
4DH
4EH
4FH
50H
51H
52H
53H
54H
55H
56H
57H
58H
59H
5AH
5BH
5CH
5DH
5EH
5FH
48
PD6461, 6462
60H
61H
62H
63H
64H
65H
66H
67H
68H
69H
6AH
6BH
6CH
6DH
6EH
6FH
70H
71H
72H
73H
74H
75H
76H
77H
78H
79H
7AH
7BH
7CH
7DH
7EHNote 2
7FHNote 3
Notes 1. Blank data 2. Display-off data (fixed at this address) 3. End code for second-byte continuous input (fixed at this address)
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PD6461, 6462
6. ELECTRICAL CHARACTERISTICS
ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage Input pin voltage Output pin voltage Operating ambient temperature Storage temperature Permissible package power dissipation (TA = 75 C) Output current Symbol VDD VIN VOUT TA Tstg PD IO 180 5
PD6461GS, 6462GS
7
PD6461GT
Unit V V V C C
- 0.3 to VDD + 0.3 - 0.3 to VDD + 0.3 - 20 to +75 - 40 to +125 320
mW mA
Caution Exposure to Absolute Maximum Ratings for extended periods may affect device reliability; exceeding the ratings could cause permanent damage. The parameters apply independently. The device should be operated within the limits specified under DC and AC Characteristics. RECOMMENDED OPERATING RANGES
Parameter Supply voltage Oscillation frequency (LC oscillation) Oscillation frequency (external clock) Operating temperature Symbol VDD fOSC fOSC TA VDD = 2.7 to 5.5 V VDD = 2.7 to 5.5 V Conditions Min. 2.7 6.0 4.0 -20 Typ. Max. 5.5 8.0 8.0 +75 Unit V MHz MHz C
ELECTRICAL CHARACTERISTICS (TA = - 20 to +75 C)
Parameter Supply voltage Supply current 1 Supply current 2 Control input high level voltage Control input low level voltage Synchronizing signal input high level voltage Synchronizing signal input low level voltage Signal output high level voltage Symbol VDD IDD IDD VCIH VCIL VISH VISL VOSH IOSL = - 1 mA (VDD = 5 V) / - 0.5 mA (VDD = 3 V) IOSL = 1 mA (VDD = 5 V) / 0.5 mA (VDD = 3 V) CKOUT IOST = - 0.5 mA (VDD = 5 V) 0.9VDD Hsync, Vsync 0.48VDD 0.16VDD fOSC = 8.0 MHz, VDD = 5.0 V fOSC = 8.0 MHz, VDD = 3.0 V DATA, CLK, CS, PCL 0.7VDD 0.3VDD Conditions Min. 2.7 Typ. 5.0 5.0 3.0 Max. 5.5 10.0 6.0 Unit V mA mA V V V V V
Signal output low level voltage
VOSL
0.1VDD
V
Oscillation output low level voltage
VOST
0.1VDD
V
Remark Signal input : DATA, CLK, CS, PCL, Hsync, Vsync Signal output: CKOUT, VR, VG, VB, VC1, VC2, VBLK, BLK1, BLK2 (RBLK, GBLK, BBLK) ( ) : Set by a mask option
50
PD6461, 6462
RECOMMENDED OPERATING TIMINGS (TA = -20 to +75 C, VDD = 2.7 to 5.5 V)
Parameter Setup time Hold time Minimum low level width of clock Minimum high level width of clock Clock cycle CS setup time CS hold time Delay from CLK to CS Minimum low level width of Hsync Minimum low level width of Vsync Symbol tSET tHOLD tCKL tCKH tTCK tCSS tCSH tDCKCS tHWL tVWL Conditions Min. 200 200 400 400 1.0 400 400 400 4 4 Typ. Max. Unit ns ns ns ns
s
ns ns ns
s s
DATA 10 % tSET tHOLD
90 % CLK 10 % tCSS tCKL tTCK tCKH
90 %
90 %
tDCKCS
90 % CS 10 % 10 %
tCSH
Hsync 10 % tHWL
Vsync
10 % tVWL
51
PD6461, 6462
POWER-ON CLEAR SPECIFICATIONS
Parameter PCL pin low level hold time Symbol tPCLL Conditions Min. 10 Typ. Max. Unit
s
VDD 0.8 VDD VDD 0V tPCLL VDD PCL 0V 0.16 VDD
EXTERNAL CLOCK INPUT Timing for external clock input (valid when selected with mask option)
Hsync tC-H
50 %
tH-C
tS 90 %
External clock
50 % 10 %
Parameter Time from external clock fall to synchronizing signal rise Time from synchronizing signal rise to external clock fall tS (rising slew rate)
Symbol tC-H
Conditions
Min. 30
Typ.
Max.
Unit ns
tH-C
30
ns
tS
Note
ns
Note 10% of the external clock cycle Example: When the external clock frequency is 8 MHz Clock cycle = 125 ns The maximum slew rate is 10% of 125 ns, giving 12.5 ns. Remarks 1. Keep the external clock in phase with the rising edges of Hsync. 2. Design the input of Hsync so that noise of more than 100 ns is suppressed. 3. When using an external clock, leave the OSCOUT pin open.
52
PD6461, 6462
CHARACTER AND BLK SIGNAL OUTPUT Character and BLK signals are output in synchronization with the falling edges of the dot clock.
50 %
Dot clock
CDL
DTW
CUS 90 %
CDS
Character signal BLK signal
50 % 10 %
OUTPUT TIMINGS (TA = -20 to +75C, pins: VR, VG, VB, VBLK, VC1, BLK1, VC2, BLK2, (RBLK, GBLK, BBLK)) Pins in parentheses are selected by specifying a mask option.
Parameter Output delay of character/BLK signal Output delay of character/BLK signal Rise time of character/BLK signal Rise time of character/BLK signal Fall time of character/BLK signal Fall time of character/BLK signal Time equivalent to minimum dot Symbol CDL CDL CUS CUS CDS CDS DTW Conditions VDD = 4.5 to 5.5 V, output load capacity = 10 pF VDD = 2.7 to 3.3 V, output load capacity = 10 pF VDD = 4.5 to 5.5 V, output load capacity = 10 pF VDD = 2.7 to 3.3 V, output load capacity = 10 pF VDD = 4.5 to 5.5 V, output load capacity = 10 pF VDD = 2.7 to 3.3 V, output load capacity = 10 pF VDD = 4.5 to 5.5 V, output load capacity = 10 pF Min. 10 15 2 4 2 4 Typ. 18 35 Max. 30 80 10 25 10 25 Unit ns ns ns ns ns ns ns
(1 /Oscillation frequency) 5Note (1 /Oscillation frequency) 5Note
Time equivalent to minimum dot
DTW
VDD = 2.7 to 3.3 V, output load capacity = 10 pF
ns
Note Min.: (1/fOSC) - 5 ns, Max.: (1/fOSC) + 5 ns fOSC: Frequency of LC oscillation or external input clock. TIMING FOR CONTINUOUS COMMAND INPUT When inputting commands continuously, the following timing requirements must be observed: (TA = -20 to +75C, VDD = 2.7 to 5.5 V)
Parameter Continuous command input timing 1 Continuous command input timing 2 Symbol T1 T2 Conditions For all commands For VRAM write commands When display is turned on When display is turned off Min. 2.0 2 s + (21/fOSC) x S +tHWL 2 s + (12/fOSC) xS Typ. Max. Unit
s s s
fOSC: Frequency of LC oscillation or external input clock (MHz), S: Character size (single (minimum) or double), tHWL: Hsync width. Commands other than VRAM write commands may not comply with T2 provided the control clock cycle satisfies the specifications.
Hi-Z DATA
Hi-Z T1 T2
Hi-Z
CLK
53
PD6461, 6462
7. APPLICATION CIRCUIT EXAMPLE
PD6461GS/GT, PD6462GS
1 (1) Connected to microcontroller 2 (2) Note 1 + 100 k 3 (4) 4 (5) 5 (6) 6 (7) Note 2 LC module pin No. 1 7(8)Note 3 LC module pin No. 3 8(9) Note 3 9(10) 10(11) CLK CS DATA PCL VDD CKOUT OSCOUT OSCIN TEST GND Hsync Vsync VB VG VR VBLK (BBLK) 20 (24) 19 (23) 18 (21) 17 (20) 16 (19) 15 (18) 14 (17) 13 (16) 12 (15) 11 (14) Output Inputs a negative Hsync, Vsync signal
VDD
10 F
10 F +
0.01 F
Note 4
VC2 Note 4 (GBLK)
Note 4
33 F
BLK2 (RBLK) VC1 BLK1
5 to 30 pF 30 pF
Notes 1. 2. 3. 4.
CR constant must be satisfied with Power-ON Clear Specification (refer to 6. ELECTRICAL CHARACTERISTICS). This circuit can reduce the number of external components and facilitates the adjustment of oscillation frequency, using LC module (part number: Q285NCIS-11181, manufactured by Toko, Inc.) Connect these pins as follows when inputting external clock: OSCIN pin: external clock input, OSCOUT pin: open Signals in ( ) are set by a mask option (RGB + RGB compatible blanking).
Remarks 1. The number in the parentheses indicates the pin number of the PD6461GT-xxx. 2. With the PD6461GT-xxx, influence by noise via lead frame can be surpressed by connecting the N.C. pins (3, 12, 13, 22) to GND.
54
PD6461, 6462
8. PACKAGE DRAWINGS
20 PIN PLASTIC SHRINK SOP (300 mil)
20 11
detail of lead end
P
1 A
10
H F G S I J
E C D
NOTE
L N S K B
ITEM A B C D E F G H I J K L M N P MILLIMETERS 6.70.3 0.575 MAX. 0.65 (T.P.) 0.32 +0.08 -0.07 0.125 0.075 2.0 MAX. 1.70.1 8.1 0.3 6.1 0.2 1.0 0.2 0.15 +0.10 -0.05 0.5 0.2 0.12 0.10 3 +7 -3 INCHES 0.264 +0.012 -0.013 0.023 MAX. 0.026 (T.P.) 0.013 +0.003 -0.004 0.005 0.003 0.079 MAX. 0.067 +0.004 -0.005 0.319 0.012 0.240 0.008 0.039 +0.009 -0.008 0.006 +0.004 -0.002 0.020 +0.008 -0.009 0.005 0.004 3 +7 -3 P20GM-65-300B-3
M
M
1. Controlling dimension millimeter. 2. Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
55
PD6461, 6462
24 PIN PLASTIC SOP (375 mil)
24 13
detail of lead end
P
1 A F G
12
H I J
L C D E
NOTE 1. Controlling dimention millimeter.
S
M
K
M
B N S
ITEM A B C D E F G H I J K L M N P MILLIMETERS 15.3 +0.41 -0.2 0.87 MAX. 1.27 (T.P.) 0.42 +0.08 -0.07 0.1250.075 2.9 MAX. 2.500.2 10.30.2 7.20.2 1.60.2 0.17 +0.08 -0.07 0.80.2 0.12 0.10 3 +7 -3 INCHES 0.602 +0.017 -0.008 0.035 MAX. 0.050 (T.P.) 0.017 +0.003 -0.004 0.0050.003 0.115 MAX. 0.098 +0.009 -0.008 0.406 +0.008 -0.009 0.283 +0.009 -0.008 0.0630.008 0.007 +0.003 -0.004 0.031+0.009 -0.008 0.005 0.004 3+7 -3 P24GT-50-375B-2
2. Each lead centerline is located within 0.12 mm (0.005 inch) of its true position (T.P.) at maximum material condition.
56
PD6461, 6462
9. RECOMMENDED SOLDERING CONDITIONS
When soldering these products, it is highly recommended to observe the conditions as shown below. If other soldering processes are used, or if the soldering is performed under different conditions, please make sure to consult with our sales offices. For more details, refer to our document "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E). Surface Mount Devices
PD6461GS-xxx: 20-pin plastic shrink SOP (300 mil) PD6461GT-xxx: 24-pin plastic SOP (375 mil) PD6462GS-xxx: 20-pin plastic shrink SOP (300 mil)
Process Infrared ray reflow Conditions Peak temperature: 235 C or below (Package surface temperature), Reflow time: 30 seconds or less (at 210 C or higher), Maximum number of reflow processes: 2 times. Peak temperature: 215 C or below (Package surface temperature), Reflow time: 40 seconds or less (at 200 C or higher), Maximum number of reflow processes: 2 times. Wave soldering Solder temperature: 260 C or below, Flow time: 10 seconds or less, Maximum number of flow processes: 1 time, Pre-heating temperature: 120 C or below (Package surface temperature). Pin temperature: 300 C or below, Heat time: 3 seconds or less (Per each side of the device). WS60-00-1 Symbol IR35-00-2
Vapor phase soldering
VP15-00-2
Partial heating method
-
Caution Apply only one kind of soldering condition to a device, except for "partial heating method", or the device will be damaged by heat stress.
57
PD6461, 6462
[MEMO]
58
PD6461, 6462
NOTES FOR CMOS DEVICES
1 PRECAUTION AGAINST ESD FOR SEMICONDUCTORS
Note: Strong electric field, when exposed to a MOS device, can cause destruction of the gate oxide and ultimately degrade the device operation. Steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. Environmental control must be adequate. When it is dry, humidifier should be used. It is recommended to avoid using insulators that easily build static electricity. Semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. All test and measurement tools including work bench and floor should be grounded. The operator should be grounded using wrist strap. Semiconductor devices must not be touched with bare hands. Similar precautions need to be taken for PW boards with semiconductor devices on it.
2 HANDLING OF UNUSED INPUT PINS FOR CMOS
Note: No connection for CMOS device inputs can be cause of malfunction. If no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar or NMOS devices. Input levels of CMOS devices must be fixed high or low by using a pull-up or pull-down circuitry. Each unused pin should be connected to VDD or GND with a resistor, if it is considered to have a possibility of being an output pin. All handling related to the unused pins must be judged device by device and related specifications governing the devices.
3 STATUS BEFORE INITIALIZATION OF MOS DEVICES
Note: Power-on does not necessarily define initial status of MOS device. Production process of MOS does not define the initial operation status of the device. Immediately after the power source is turned ON, the devices with reset function have not yet been initialized. Hence, power-on does not guarantee out-pin levels, I/O settings or contents of registers. Device is not initialized until the reset signal is received. Reset operation must be executed immediately after power-on for devices having reset function.
59
PD6461, 6462
[MEMO]
The application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
No part of this document may be copied or reproduced in any form or by any means without the prior written consent of NEC Corporation. NEC Corporation assumes no responsibility for any errors which may appear in this document. NEC Corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. No license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of NEC Corporation or others. While NEC Corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. To minimize risks of damage or injury to persons or property arising from a defect in an NEC semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. NEC devices are classified into the following three quality grades: "Standard", "Special", and "Specific". The Specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. The recommended applications of a device depend on its quality grade, as indicated below. Customers must check the quality grade of each device before using it in a particular application. Standard: Computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. The quality grade of NEC devices is "Standard" unless otherwise specified in NEC's Data Sheets or Data Books. If customers intend to use NEC devices for applications other than those specified for Standard quality grade, they should contact an NEC sales representative in advance. Anti-radioactive design is not implemented in this product.
M4 96.5

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